It is confusing but I believe they use ASSP and ASIC to differentiate tool flows (ASIC vs. Foundry)
Sounds like MSFT did their own chip design with their own libraries /timing models/polygons/etc and qualed/tested it themselves (Foundry Flow).
Anyone who knows ASICs knows the ASIC vendor has you by the short and curlys as the design is not easily portable. MSFT wanted to avoid this.
Looks like they blew the design and went to ATI to use their IP and more importantly, back-end flow. I don’t think ATI did a chip just for MSFT.
Cisco does their own ASSPs and pulls it off. I think MSFT made a good decision but had execution issues. I am sure they will redesign the ASIC into an ASSP again but they needed a quick solution. That’s what happens when you let the software guys do the hardware.
* interesting usage of ASSP and ASIC
* Shouldn’t it be that MSFT tried to do their own ASIC and blew it. Then went the ASSP route.
* All-in-all great newsbite for ASSP vendors!
It is confusing but I believe they use ASSP and ASIC to differentiate tool flows (ASIC vs. Foundry)
Sounds like MSFT did their own chip design with their own libraries /timing models/polygons/etc and qualed/tested it themselves (Foundry Flow).
Anyone who knows ASICs knows the ASIC vendor has you by the short and curlys as the design is not easily portable. MSFT wanted to avoid this.
Looks like they blew the design and went to ATI to use their IP and more importantly, back-end flow. I don’t think ATI did a chip just for MSFT.
Cisco does their own ASSPs and pulls it off. I think MSFT made a good decision but had execution issues. I am sure they will redesign the ASIC into an ASSP again but they needed a quick solution. That’s what happens when you let the software guys do the hardware.
“software guys doing hardware” …. good phrase. Can you say NPU